The present invention relates to a circuit for comparing the magnitudes of two n-bit binary signals each being constituted by an n-bit binary number (n=1, 2, 3 . . .).
A circuit for comparing binary signals of the kind described has customarily been constructed and integrated by combining a plurality of logic gates such as AND gates and NAND gates. Typical of prior art comparing circuits is a .mu.PD4063BC/4063BG which is disclosed in "CMOS DIGITAL IC 1986" published Dec. 10, 1985, pp. 147 to 151. The binary signal comparing circuit produces either a logical 1-bit signal of ONE or ZERO depending upon whether one of two binary signals is greater or smaller than the other.
A drawback with the prior art comparing circuits for the above application is that several ten logic gates are required to compare 4-bit binary numbers and, hence, such a circuit cannot be integrated without needing a prohibitive number of transistors. The result is an increase in current consumption as well as in chip area required. In addition, when the number of bits of each binary signal is increased, wiring becomes complicated making the design of an integrated circuit difficult.